Peripheral Interface Adapter

• 8-Bit Bidirectional Data Bus for Communication with the MPU
• Two Bidirectional 8-Bit Buses for Interface to Peripherals
• Two Programmable Control Registers
• Two Programmable Data Direction Registers
• Four Individually Controlled Interrupt Input Lines; Two Useable as Peripheral Control Outputs
• Handshake Control Logic for Input and Output Peripheral Operation
• High-Impedance Tri-State and Direct Transistor Drive Peripheral Lines
• Program Controlled Interrupt and Interrupt Disable Capability
• CMOS Drive Capability on Side A Peripheral Lines
• Two TTL Drive Capability on All A and B Side Buffers
• TTL Compatible
• Static Operation

(Data taken from Motorola Semiconductors MC6821 Datasheet)